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Phase Change Memory

Phase Change Memory (PCM) technology is based on the basic properties of the chalcogenide alloy1, so the integration of the material into a standard CMOS process represents a challenging matter: not for the single cell concept, already proven to be very strong, but for the manufacturability of very high density non-volatile memory, where the technology can be considered robust only if demonstrated over many billions of cells. Considering the electronic and transport properties of the chalcogenide alloy, either in the crystalline or in the amorphous state, in order to form a functional compact cell array, a PCM cell is be formed by a variable resistor (heater and chalcogenide – called>

Figure FEP14 Amorphous / Poly-crystal Phases of a Chalcogenide Alloy, usually Ge2Sb2Te5 (GST)

Figure FEP15 Resistance Change of GST



Figure FEP16 Set/Reset Thermal Cycles to Change the Crystal Phase of the GST Material
and to Write/Erase the PCM

The integration of the>A completely different approach relies on the definition of the contact area between the heater and the chalcogenide by the intersection of a thin vertical semi-metallic heater and a trench, called a “trench,”7 in which the chalcogenide is deposited. Since the trench can be defined by sub-litho techniques and the heater thickness by film deposition, the cell performance can be optimized by tuning the resulting contact area still maintaining a good dimensional control. Table FEP8 summarizes the main technology requirements for Phase Change Memories.

Table FEP8 Phase Change Memory (PCM) Technology Requirements

Despite the high potential of the PCM concept and the good integration results so far achieved,8, 9 some practical challenges must still be addressed. In particular, large efforts are being dedicated to the integration of a compact PCM cell structure with the chalcogenide compound, to achieve a full compatibility with an advanced CMOS technology and to reduce the programming current without degrading the appealing features of the PCM technology. The easier integration of PCM cell is achieved with the pillar-like structure, but the resulting programming currents are quite large, thus posing additional constraints on the selecting device and on the overall power consumption. Several approaches so far proposed to reduce the programming currents of PCM devices rely on the confinement of the chalcogenide compounds in trenches,10, 11 contact recessions,12 or contact holes.13 The main idea is to force the maximum current crowding directly in the active region of the cell, where the chalcogenide material switches between the two phases. In fact, it has been estimatedError: Reference source not found that the programming currents can be reduced up to the 50% by employing fully confined structures with the chalcogenide material that fills a contact hole. The superior capabilities of confined structures has been demonstrated by the µTrench PCM cell architecture that achieved a programming current of 450 µA at 180 nm14and 350 µA at 90 nm.15A programming current of 260 µA in a 50 nm contact has been demonstrated for a fully confined structure obtained with a CVD-deposited chalcogenide.16 These results point out that the fabrication of efficient PCM cell architectures will be required to fill confined structures with very high aspect ratio. A continuous improvement of the chalcogenide material minimum conformality is thus expected to support the cell architecture evolutions.

To support reliable large array products, PCM technologies must be able to retain data over the product’s lifetime with very low defect rates. Data retention is limited by resistance loss of the amorphous phase of the material, a process that is controlled by the kinetics of crystallization. Prior work on data retention of reset cells shows that data retention of GST is much longer than ten years at 85°C, and therefore adequate for typical non-volatile memory applications.17,18 This value is satisfactory to address consumer applications, but it is not matching industrial requirements for high temperature operation (e.g., automotive applications). This drives a need for improvement of the maximum storage temperature. This improvement will mainly come from the development of different chalcogenide compounds and compositions.

Memory of a broken dimension mac os 8

One of the most attracting features of PCM technology is the expected superior endurance when program and erase repetitive operation are performed. Several publications reports endurance capabilities that range from 107 up to 1012 cycles. Such impressive results depend on the intrinsic endurance of the chalcogenide compounds as well as on the overall stability of the PCM cell surrounding material. Among them, the heater electrode is the part of the cell that undergoes to the heavier stressing conditions, with temperatures much higher than the 600°C and current densities that can exceed 1 A/m2. The most important electrical property of the heater material that must be preserved during cycling is the electrical resistivity, which is to remain stable according to the endurance requirement. The maximum resistivity variation is thus intended to provide a guideline on the main electrical property of the heating element in PCM cells, providing the requirement that guaranties to be able, with the same current, to switch the PCM cells among the two logic states for the required number of P/E cycles.

The requirement on the heater resistance stability is intimately related to the maximum reset current density requirement. It has been reported that, under the simple assumption of isotropic scaling, the expected reset current density will increase linearly with the scaling factor,Error: Reference source not found and a more aggressive trend could be expected according to the forecasted roadmap. A detrimental effect of this increase could be more aggressive stressing conditions for the heater material and for the chalcogenide-heater interface, which should be faced with a slower growth of the required current density. It follows that a better heating efficiency will be required to downscale the PCM devices that could be achieved through an increase of the heater resistivity, still preserving the stability requirements. It is thus expected that the scaling roadmap of PCM technology will face the need to provide novel material for the heating electrode capable to reach a trade off among the endurance requirements and the performance requirements.

  1. Ferroelectric Random Access Memory (FeRAM)

FeRAM (also abbreviated FRAM) was a new addition to the 2001 ITRS, and was the result of collaboration between the FEP and PIDS technology working groups. The critical requirement tables, Table FEP9, was revised in 2009 based on the results of a survey of the FeRAM manufacturers.

Table FEP9 FeRAM Technology Requirements

Historically speaking, FeRAM devices had been proposed much earlier than semiconductor memories19. At present however, memory capacity is limited to ~1/1000 of that of commodity DRAM, due to difficulties associated with capacitor fabrication, integration, and reliability. Though these difficulties together with the lack of a “killer application” had constrained commercial production, recently several “killer applications” are proposed. Solid state drive (SSD) is one promising application. In this case, FeRAM acts as page buffer memory instead of DRAM and /or SRAM, thus utilizing FeRAM high speed write/read performance and non volatility.

FeRAMs depend substantially on the continued development of materials such as ferroelectric films which make forecasts presented here somewhat speculative. Nevertheless, the roadmap covers the years 2009 to 2024 in order to provide a strategic overview of the technology directions and the challenges that must be overcome. This section consists of 1) mass production based table, 2) mixed-signal devices and feature size, 3) cell size, 4) ferroelectric materials alternatives, 5) minimum switching charge estimation, and 6) endurance.

  1. Mass Production Based Table

Since the FeRAM table was introduced in 2001, the requirements that have been included in the tables from 2001–2006 reflected FeRAM technology that was presented at conferences because obtaining accurate information on devices in the marketplace was not readily available. As a result, a large gap existed between what FeRAM semiconductor manufacturers presented at conferences and what was commercially available on the market. To eliminate this gap, the requirements for the 2007 table were defined from the manufacturer’s requirements available on their homepage, surveys, and using a previous precedent established for DRAMs, where the level of technology in the roadmap is based upon the two leading manufacturers which have achieved a production volume of at least 10,000 chips per month. The 2009 table is defined as the same manner with the 2007 table based on FeRAM mass production information.

  1. Mixed Signal Devices and Feature Size

As noted above FeRAM technology has lagged behind leading edge memories such as Flash and DRAM. Although this gap exists, manufacturers have developed devices which use advanced CMOS such as 0.13µm technology but use 0.18 µm technology for the Metal 1 half pitch width for FeRAM as shown in Table FEP9. The FeRAM technology node is defined here by Metal 1 half pitch width for this roadmap. Combining advanced CMOS technology with relaxed designed rules for FeRAM, is expected to increase the number of applications for FeRAM. Table FEP9 shows a feature size of 0.18µm for year 2009 commercial product using the same criteria as DRAM. Feature size scaling is forecasted to occur at approximately 0.8 every four years which is at a slower pace than other established memories. Grow (itch) (raespark) mac os.

  1. Cell Size

Memory Of A Broken Dimension Mac Os 7

Currently, the most efficient cell structure is the One Transistor-One Capacitor (1T-1C) cell and it is replacing the 2T-2C cell that is less efficient but offers greater operating range stability as noted in a recent review on FeRAM design.20 However, in the market both cell structures will likely be available for some time depending upon the device application. As far as the capacitor structure is concerned, the change from the planar capacitor type to a stack configuration has resulted in a cell size reduction. The timing of a shift from a stacked structure to a 3D structure will depend upon the ferroelectric material used and it is expected to occur approximately in 2016. The different capacitor configurations are shown in the drawing accompanying Table FEP9. The above-mentioned cell structure and capacitor configuration changes are forecasted to reduce the cell area factor to 16 in years 2013–2015 after which the cell area factor will continue with further scaling. Another path to shrink the cell size is by changing to a one transistor type (1T). Basic research and development are continuing on this topic.

  1. Ferroelectric Materials Alternatives

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There are several ferroelectric materials under evaluation at the present time21 , but there is no clear, single material choice. The two current materials are PZT, or Pb(Zr,Ti)O3 and SBT, or SrBi2Ta2O9. SBT has superior fatigue-free characteristics with a Pt bottom electrode and is more suitable for low voltage operation because of its smaller coercive field (Ec). (Fatigue is defined as a loss of polarization or charge that develops after bipolar cycling of the memory capacitor.) PZT has a larger switching charge per unit area, QSW, which is important since it is allows for further scaling without shifting to a 3D cell. Both materials may suffer damage due to process integration during the device fabrication which has hampered device development.

The most important issues with PZT and SBT films are suppression of film deterioration that is attributed to hydrogen diffusion22 and oxygen loss, the achievement of stable data read/write characteristics, and data retention during integration. Process improvements are also required for embedding FeRAM. It is important to avoid high temperature annealing or hydrogen incorporation into ferroelectric films after the oxygen anneal used to crystallize the films. For example, AlOx and TiN are often used as hydrogen barrier layers. Also, conductive oxides such as IrO2 or SrRuO3 (SRO) are often used as capacitor electrode materials for PZT since their use improves ferroelectric capacitor reliability.

Physical vapor deposition (PVD) and chemical solution deposition (CSD) including Sol-Gel methods are the most commonly used methods for ferroelectric film deposition. However, continued scaling dictates the need to shift to methods with better step coverage such as MOCVD as noted in Figure 14. A previously reported MOCVD study has shown that a (111) oriented PZT film is very effective at increasing the switching charge.23 Etching of capacitor electrodes remains a challenge with RIE, because the capacitor electrodes do not react to form volatile etch by-products. Therefore, sputter etching is widely used. This limits critical dimension (CD) control and makes scaling more difficult. High temperature etching technology for improving sidewall slope of the capacitor was developed to overcome this difficulty.24

PZT and SBT are often doped to improve their electrical properties. For instance, PZT may be doped with lanthanum and SBT with niobium. Doping is used to achieve the following film enhancements: leakage current suppression, improved endurance or imprint characteristics, suppression of post process film degradation, and others. Besides PZT and SBT, one of the promising new materials is BLT or (Bi,La)4Ti3O12,25 of which characteristics are in-between the foregoing two.26 In addition, BiFeO3 (BFO) has gained much attention as a new candidate material. BFO has a giant ferroelectric polarization of 150C/cm2 or more.27 Although BFO exhibits a large polarization, it also requires a higher switching voltage which means that the film needs to be thinner or possibility doped to accommodate low voltage operation. Since the ferroelectric properties of each material have improved in recent years due improvement in process technology, it essential for the process to be optimized for the integrated ferroelectric capacitor in order to obtain good ferroelectric properties.

  1. Estimated Minimum Switching Charge

The estimated minimum switching charge has been derived as follows: The sense amplifier for FeRAM is assumed to be basically the same as that of DRAM. Therefore, the bitline signal voltage was calculated using DRAM data from the 1999 ITRS. These data provide that the capacitance Cs remain constant at 25fF/cell independent of technology node, and the bitline capacitance is 320fF at the 0.18 µm node. Based on this data with the further assumption that bitline capacitance is proportional to F2/3, where F is the feature size28 allows for the calculation of Vbitline. The Vbitline is about 140 mV, and the assumption is that this is needed for the sense amplifier circuit independent on technology nodes. Multiplying Vbitline (140 mV) with Cbitline then gives the minimum switching charge.

Dividing the minimum switching charge value derived above by the ferroelectric film switching charge per unit area, QSW, (assumed to be 30 µC/cm2) then yields the desired capacitor area. If this area is larger than the projected capacitor size, then a 3D capacitor should be adopted. Scribblehead mac os. Based on this, a 3D capacitor will be needed by year 2017.

The FeRAM forecast of Table FEP9 is based on these assumptions and calculations. “Red brick walls” begin to appear in 2017. The first priority to break through these walls is the development of highly reliable ferroelectric materials that exhibit negligible process induced degradation.

  1. Endurance

An endurance of 1015 read/write cycles is required to replace other RAMs such as SRAM and DRAM. In order to confirm such endurance values, standardized testing within a practical time period is needed based upon accelerated testing methods with an underlying physical model is needed. There are several models in the literature on degradation of ferroelectric capacitors due to endurance testing but so far there are few reports on degradation on integrated capacitors.

Recently, FeRAMs are being used for IC cards and the personal authentication, etc. utilizing the feature of fast program speed and high endurance instead of EEPROM or FLASH memory. Security applications show strong potential to be a growing market for FeRAM.

Figure FEP14 FeRAM Potential Solutions

  1. Starting Materials
    1. Technology Requirements

Table FEP10 forecasts trends for starting wafers produced by silicon wafer manufacturers that are intended for use in the manufacture of both high density memories such as DRAMs and high-performance MPUs and ASICs. These requirements include parameters common to all wafers plus parameters specific to epitaxial and SOI wafers. Fundamental barriers presently limit the rate of cost-effective improvement in wafer characteristics such as localized light scatterers (LLS) defect densities, site flatness values, and edge exclusion dimensions. These barriers include the capability and throughput limitations of metrology tools, as well as wafer manufacturing cost and yield issues fundamental to the crystal-pulling process and subsequent wafer finishing operations. Accordingly, use of the methodology introduced in the 2005 edition of the ITRS, to display not only the ability of the wafer supplier to meet the parameter trends in Table FEP10, but to also display the metrology tool readiness, is continued. The marking system and meanings are shown in the tables for both DRAM and high-performance MPUs / ASICs. Additionally, the hyperlink which addresses metrology by providing further relevant information is again included. (Link to Metrology chapter.)

Table FEP10 Starting Materials Technology Requirements

  1. Wafer Types

For the device types included in the scope of the ITRS,starting materials selection historically involved the choice of either polished Czochralski (CZ) or epitaxial silicon wafers. However, silicon-on-insulator (SOI) wafer usage continues to show growth, although the total number of SOI wafers shipped is still small compared to polished and epi wafers. The prospect for SOI wafers to be used in mainstream, high-volume applications is being driven by improved high-frequency logic performance and reduced power consumption. Further opportunity is afforded with enhanced device performance via unique device configurations such as multiple-gate structures, but these require additional development of both the wafer and device processes in order to achieve practical volume production. In some cases, device process flow simplification is also achieved with SOI. Therefore, the selection of wafer type is based strongly on performance versus overall cost per die and should include all aspects for consideration, not just starting wafer price. It should also be noted that successful adoption of multiple-gate structures on non-SOI have been reported, so segmentation of wafer types continues to be the trend for the foreseeable future.

Commodity devices such as DRAM are commonly manufactured on lower cost CZ polished wafers. The elimination of “crystal originated particles” (COP) in CZ polished wafers is increasingly required to avoid interference with inline inspections used for defect reduction and yield enhancement. Please note that the term “particle” may seem misleading because the structure of the defect is actually pit-like. However, these defects where initially observed by automated particle scanning equipment, thus the term “particle” is utilized as the historical reference. High-performance logic ICs are generally manufactured on more costly epitaxial wafers (compared to polished CZ wafers) because their use has facilitated the achievement of greaterrobustness (e.g., soft error immunity and latch-up suppression capability). The latter capability may no longer be as critical due to the implementation of shallow trench isolation (STI) and the development of alternate doping methods for achieving latch-up suppression. Additionally, partially depleted SOI has been adopted for certain types of high performance logic ICs and development work is ongoing for fully depleted SOI.

Annealed wafers were introduced in the early 1990s as an alternative means to provide a silicon wafer with a COP-free surface and are now used for many leading-edge device applications. Annealing occurs in either a hydrogen (/U> 200 mm wafer diameter) or an argon ambient at high temperatures. COPs can also be controlled by appropriately engineered CZ growth methodologies. For the purpose of the Starting Materials table presented here, annealed wafers and “defect engineered CZ” are both considered forms of polished CZ wafer and have parameter trends noted in the General Characteristics sections.

This wide variety of starting materials will likely continue into the foreseeable future and accounts for inclusion of general as well as specific epitaxial and SOI wafer characteristics in Table FEP10. Emerging materials that may further augment the variety of starting materials are discussed later in this document.

  1. Parameter Values

Wafer requirements have been selected to ensure that in any given year each parameter value contributes no more than 1% to leading-edge chip yield loss. The values in the table are generally, but not exclusively, derived from probabilistic yield-defect models. These models take into account leading-edge technology parameters such as critical dimension (CD)taken as the DRAM half-pitch (i.e., the technology generation)bit density, transistor density, and chip size. The validity of these derived values is limited by the sometimes questionable accuracy and predictability of the underlying models. With the onset of nanometer device dimensions for both the gate dielectric equivalent oxide thickness and the device physical channel length, compliance with these model-based values can be very costly and, in some cases, requires re-examination. For this reason, detailed re-assessment of the costs incurred versus the value derived from achieving compliance often suggests limiting the scope of these models via appropriate truncation.

  1. Model Limitations

Such model-based parameter requirements do not include effects of distribution of parameter values intrinsic to the wafer manufacturing process where either of two statistical distributions commonly apply. Parameter values distributed symmetrically around a central or mean value, such as thickness, can often be described by the familiar normal distribution. The values of zero-bounded parameters (such as site flatness, particle density, and surface metal concentration) can usually be approximated by a lognormal distribution, in which the logarithms of the parameter values are normally distributed. The latter distribution is skewed with a long tail at the upper end of the distribution. Validation of the yield models remains elusive despite the experience of more than forty years of IC manufacturing.

The ideal methodology for management of material-contributed yield loss would be to allocate loss by defect type such that these do not contribute more than 1% to the overall IC fabrication yield loss. Yield loss for a particular defect is equal to the integral of the product of 1) the probability of failure due to a given value of the parameter (as established by the appropriate yield model) and 2) the fraction of wafers having that value (as established by the normal or lognormal distribution function). By applying this methodology, one could determine acceptable product distributions. Successful implementation of a distributional specification requires that the silicon supplier’s process is sufficiently well understood, under control, and capable of meeting the IC user requirements. Until these ideals can be achieved, however, Poisson Distribution yield models based on the best available information are used and parameter limits assigned based on a 99% yield requirement for that parameter. It is further assumed that the yield loss from any individual wafer parameter does not significantly contribute to the yield loss from any other parameters, that is, that the defect yield impacts are statistically independent. Where validation data are available, this empirical approximation has been shown to result in requirement values nearly equal to the limit values obtained from the aforementioned methodology using parameter distributions.

  1. Cost of Ownership (CoO)

As the acceptance values for many parameters approach metrology limits, enhanced cooperation between wafer suppliers and IC manufacturers is essential for establishing and maintaining acceptable product distributions and costs. Further development and validation of IC yield/defect models is required. However, it is essential to balance the “best wafer possible” against the CoO opportunity of not driving wafer requirements to the detection limit defined by acceptable metrology practice, but instead to some less stringent value consistent with achieving high IC yield. For example, the surface metal and particle contamination requirements for starting wafers are less stringent than the pre-gate values given in the Surface Preparation section (see Table FEP11) because it is assumed that a minimum cleaning efficiency of 50% (actually 95% has been reported for surface iron removal) results during IC processing steps such as the pre-gate clean. It is also noted that the chemical nature of the surface requested by the IC manufacturer (hydrophilic versus hydrophobic) and the wafer-carrier interaction during shipment as well as the humidity in the storage areas are important in affecting the subsequent adsorption of impurities and particles on the wafer surface. Further emphasis on the CoO has been ascertained by developing a model examining the viability of a 100% wafer inspection to a particular parameter (i.e., site flatness). This model considers the wafer supplier’s additional cost of ensuring 100% compliance to the IC manufacturer’s specification relative to the potential loss associated with processing a die with a high probability of failing if a 100% inspection is not done. The relevant worksheets employing this methodology are available as links to this chapter so that each IC manufacturer can analyze the trade-off appropriate for their wafer specifications and product family of interest.

  1. Wafer Parameter Selection

Both the chemical nature and the physical structure of the wafer front surface are of critical concern. Parameters related to the former are not included in Table FEP10 due to lack of appropriate model-based definitions. Chemical defects include metal and organic particles and surface chemical residues. These defects are equally significant for all wafer types, although there is some concern that the detrimental effects of surface metals may be magnified in ultra-thin SOI films when the metals diffuse into a small silicon volume. Organic contamination strongly depends on environmental conditions during wafer storage and transportation, and accordingly is not included in Table FEP10.

With the adoption of double-side polished wafers, attention is also being given to particles on the back surface of the wafer to improve both the chemical and physical characteristics. The polished back surface more readily exhibits microscopic contamination and wafer handling damage. As a result, back-surface cleanliness requirements may emerge and drive the need for more stringent robotic handler standards. However, based on a past Starting Materials IC Users Survey, site flatness degradation due to the presence of back-side particles does not currently appear to be of significance and has not been included in this edition of the ITRS. In addition, any back-surface treatments (e.g., extrinsic gettering and oxide back seal) may degrade the quality of both the polished back- and front-surfaces and are generally not compatible with standard wafer manufacturing approaches at diameters > 200 mm.

Important physical characteristics of the wafer front surface include topography, structural defects, and surface defects. Wafer topography encompasses various wafer shape categories that are classified according to their spatial frequency as site flatness, surface waviness, nanotopography, or surface micro-roughness. Front surface site flatness and nanotopography are believed to be the most critical of the topographic parameters and are therefore again addressed in this ITRS revision. Quantification of back surface topography has received more attention in view of the possible interaction with stepper chucks. While technology for quantifying this interaction has improved, we lack accepted models to include as table values at this time. Near-edge wafer geometry is also emerging as a potential yield-limiting attribute for silicon wafers. Often referred to as edge roll-off (ERO), it encompasses a variety of angularly and radially varying features in the region of the wafer surface between the substantially flat major central region of the wafer and the edge profile (the intentionally rounded outer periphery of the wafer). Industry consensus has greatly advanced allowing for standardization of ERO parameters (SEMI M67: ESFQR; SEMI M68: ZDD). Further, ERO metrology guidelines through the 22nm technology generation are available in SEMI M49. However, additional agreement is needed in order to establish ERO-related trend values for future technology generations.

Structural defects include grown-in microdefects, such as COPs and bulk microdefects (BMDs). Methods of COP control have been discussed above. With advanced silicon manufacturing techniques, BMDs can be controlled independently of the interstitial oxygen concentration. In addition, current fab thermal cycles use lower temperatures and shorter times, and are not suitable to produce high levels of BMD for intrinsic gettering. As a result, in applications for which the customer is depending on BMD for gettering, a careful discussion of options with the silicon supplier is required

Other starting material requirements are expressed in terms of specific types of surface defects for different wafer types. Recent data suggest that certain devices (such as DRAM) produced on polished wafers may be sensitive to very shallow small scratches and pits. Epitaxial and SOI materials appear to exhibit fewer surface defects of this type. On the other hand, epitaxial and SOI wafer defects include large structural defects (arbitrarily defined as > 1 m) and small structural defects (< 1 m). Epitaxial wafers are subject to grown-in crystallographic defects such as stacking faults, and large defects created by particles on the substrate. Such defects must be controlled to maximize yields when using epitaxial wafers. Several defects are unique to SOI wafer. Large area defects are of the greatest concern to yield, and include voids in the SOI layer and large defects of the SOI/BOX interface. These large defects are judged to have a serious effect on chip yield and are assigned a kill rate of 100%. Smaller defects, such as COPs, metal silicides or local SiO2 islands in the top silicon layer (measured in tens of nanometers to tenths of microns) are believed to have a less severe impact on device performance and thus the allowable density is calculated based on a lower kill rate. The development of laser scanning and other instrumentation to count, size, and determine the composition and morphology of these defects is a critical metrology challenge. While threshold size for detection continues to enjoy improvements, compositional and morphological segregation remains insufficient. As such, the removal and prevention of surface defects continues to be a state-of-the-art challenge for silicon wafer technology.

The dependence of gate dielectric integrity and other yield detractors on crystal growth parameters as well as the related role of point defects and agglomerates have been extensively documented. The resulting defect density (Do) parameter has served effectively as a measure of material quality for several device generations. However, for devices with EOT < 2 nm, this parameter is no longer an indicator of device yield and performance and is accordingly been not included in Table FEP10 as a requirement. It should be noted, however, that starting material cleanliness requirements might change if pre- and post-gate surface preparation methods are modified when high- gate dielectric materials are introduced (see Surface Preparation section).

Metrologyfor SOI wafers is a significant challenge. Optical metrology tools operating at visible wavelengths do not have the same capabilities for characterizing SOI wafers as they have with polished or epitaxial wafers. Interference effects arising from multiple reflections from the Si and BOX layers fundamentally alter the response of these tools compared to polished and epitaxial wafers, generally degrading the measurement capability. UV/DUV wavelength optical tools have been shown to help alleviate these difficulties at least for top silicon layers thicker than 10 nm, because of the much shorter optical absorption depth at these wavelengths. Metrology methods for many of the SOI defect categories call for destructive chemical etching that decorates, but does not uniquely distinguish, various types of crystal defects. These various defects may not all have the same origin, size, or impact on the device yield and, therefore, may exhibit different kill rates. Additionally, decorative defect etching on SOI wafers with very thin top silicon layers is very difficult because of the extremely small etch removals that must be used to avoid completely etching away the entire layer under inspection. Non-destructive and fast-turn around methods are also needed for the measurement of electrical properties and structural defects in SOI materials. Finally, the metrology issues for the various strained silicon configurations (spatially varying strain levels and Si:Ge composition, threading dislocations and associated defects as well as unique surface roughness issues) require significant efforts (see the Emerging Materials section below).

Memory Of A Broken Dimension Mac Os Catalina

Layer thickness and uniformity are included in Table FEP10 for SOI wafers. For such wafers, the broad variety of today’s IC applications requires a considerable range of Si-device layer and buried oxide (BOX) layer thicknesses. A number of SOI wafer fabrication approaches have entered production to serve this range of SOI applications. In some cases this includes strained SOI (sSOI), which has the same layer structure as conventional SOI, except the Si film is under biaxial tensile strain that increases the electron mobility, and to much lesser extent, the hole mobility. Strained Si is discussed in more detail in the Emerging Materials section of this chapter. The table gives incoming silicon thickness for both partially depleted (PD) and fully depleted (FD) devices. While the PD thickness values are extended shown through 2018 and removed thereafter, it is expected that similar characteristic trends will be required for multi-gate devices and therefore may be reintroduced at a later time, depending on the progress of such adoption. For instance, in the first order, these PD values are consistent with expected silicon thickness values for such multi-gate devices. Also, in order to be consistent with actual manufacturing practices within the industry, FD thickness values prior to 2010 remain absent from Table FEP10.

Memory Of A Broken Dimension Mac Os Sierra

  1. Potential Solutions

Figure FEP15 lists the most significant starting materials challenges and shows potential solutions that have been identified, along with the necessary timing for development of these solutions and their transfer into high-volume production. In alignment with Table FEP10, Figure FEP15 reflects the requirements of leading edge DRAMs and high-performance MPUs, built on 300 mm (or larger) diameter wafers. It should be noted however that application of 200 mm wafers beyond the 90 nm technology generation continues in some instances and requires double-side polishing to achieve the necessary flatness and nanotopography levels. Implementation of this wafer type will require additional investments from both the wafer suppliers and users.

  1. Material Selection

The materials selection category is divided into two sections—defect engineered CZ and SOI wafers. The type of material chosen depends strongly on the IC application and cost performance optimization. The former is typically utilized for cost-sensitive applications while the latter is used for performance-sensitive applications. As noted in Figure FEP15, potential solutions are diverging, which will result in a greater challenge to available resources.

  1. Emerging Materials

The utilization of materials solutions, Emerging Materials, that augment other methods to meet ITRS targets remain critically important to the future of the silicon industry. For the 2011 ITRS, three distinct categories of Emerging Materials have been identified: 1) thermal management solutions, 2) mobility enhancement solutions, and 3) system-on-chip solutions. Examples of emerging materials that could potentially provide thermal managements solutions (i.e., improve heat dissipation properties) for future microelectronics applications include Si-on-Diamond and Si-on-insulator with the insulator being a material of higher thermal conductivity than SiO2, for example Al2O3 (alumina) or silicon nitride. In addition to concerns regarding heat dissipation, future microelectronic systems will feature transistor channels that have greater mobility than that of Si. Among those emerging materials potential solutions targeted at enhancing channel mobility are strained Si, germanium (relaxed and strained), and carbon nanotubes. Lastly, the ability to integrate new functionality into traditional CMOS logic architecture can be enabled by emerging materials innovations as well. High resistivity Si substrates and monolithic optical interconnection on Si are potential system-on-chip solutions. These emerging material topics, although potentially providing technical solutions to critical challenges facing future microelectronics, lack the maturity to include detailed requirements in Tables FEP10 for this year’s ITRS revision. However, these topics will continue to be tracked and the Emerging Materials sub-committee of the ITRS Starting Materials team has assembled a detailed set of notes and references for the reader online.

  1. Wafer Diameter

Productivity enhancement has historically been achieved partially by wafer diameter migration. The transition from 200 mm to 300 mm occurred at a time when the industry was facing serious economic challenges. This substantially delayed the onset of high-volume manufacturing for that diameter versus the expected timing based on the historical cycle. This has already influenced the timing of the potential move from 300 mm to 450 mm. The need for next-generation 450 mm silicon substrates to continue productivity gains poses an important economic challenge. Based on historical diameter change cycles, the industry is already several years behind the pace to prepare the next-generation 450 mm silicon substrate for device manufacturing in 2014, though recent announcements should accelerate the efforts. Issues related to 450 mm silicon wafer introduction have been compiled separately in a 450 mm position paper available online.

  1. Site Flatness

The industry made a substantial gain in site flatness process capability by going to double-sided polish for 300 mm wafers. Incremental improvements on this basic gain are expected to satisfy IC manufacturers’ requirements to approximately the 20 nm technology generation. Continued improvement beyond that point may require the implementation of new flatness-improvement technologies, including those discussed in Figure FEP15 and its accompanying text. However, next generation lithography may strongly impact the actual flatness requirements. The potential adoption of EUV, for instance, is an important consideration. Depending on the Numerical Aperture (NA) of the system, the trend values presented in the roadmap appear to be sufficient, or possibly overstated. Further, an understanding of site flatness requirements for new device structures (such as multi-gate) is needed, in order to correctly model requirement trends.

Figure FEP15 Starting Materials Potential Solutions

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